Senior SoC Design Verification Architect | DV Lead

A semiconductor startup in Sunnyvale is seeking a Principal Design Verification Engineer to lead a team in the verification of complex IPs and SoCs. The ideal candidate should have 12 to 15 years of experience in ASIC design verification, expertise in SystemVerilog and UVM methodology, and strong leadership abilities. Responsibilities include establishing verification plans, driving alignment across teams, and debugging complex issues. The position offers a competitive compensation range of $250,000–$280,000 per year, with benefits including medical, dental, and stock options.
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