Senior Design Verification Engineer - High-Perf IP & NoC

A leading technology firm in San Jose is seeking a Design Verification Engineer to join its Internal IP DV team. The ideal candidate will develop UVM/SystemVerilog testbenches and ensure robust high-performance custom IPs. Candidates should possess strong debugging skills and knowledge in computer architecture. The role includes collaboration with various teams to validate functionality. Competitive medical and wellness benefits are offered, alongside a housing subsidy and relocation support.
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