Senior Design Verification Engineer – SoC/IP, UVM & LLM Tools

A leading technology company seeks a Design Verification Engineer in Melbourne, Florida. This role involves ensuring bug-free silicon for SoC/IP products, developing comprehensive test plans, and utilizing verification methodologies. Candidates should have a BS degree and at least 10 years of industry experience, along with extensive knowledge of SystemVerilog, UVM, and LLMs. The company promotes inclusion and diversity in hiring.
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