Design Verification Engineer — Deliver Bug-Free First Silicon

A leading technology company in Beaverton, Oregon is seeking a hardworking Design Verification Engineer. In this role, you will ensure bug-free first silicon for part of the SoC/IP, developing verification methodology and environments. Candidates should have a Bachelor's degree in a technical field and experience in SystemVerilog and UVM. The position offers a unique opportunity to work on innovative projects in a collaborative environment, with a commitment to diversity and equal opportunity.
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