Senior ASIC Design Engineer - HBM/LPDDR Memory Subsystems

A leading technology firm is seeking a Senior ASIC Design Engineer located in California. The candidate will be responsible for designing high-speed memory subsystems for next-generation products, requiring over 5 years of experience in ASIC design and RTL coding. Responsibilities include architecture, design, verification, and debugging, ensuring high-quality and efficient designs. The position offers a competitive salary range of $140,000 to $210,000 alongside various benefits.
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