Hybrid RTL Design Engineer – DRAM Power & PPA Focus

A leading semiconductor firm located in Boise, Idaho, is looking for an RTL Build Engineer to develop DRAM digital blocks focusing on power efficiency. You'll work hands-on with tools for power, performance, and area evaluations while collaborating with multifunctional teams to enhance product quality. Applicants should have a Master's degree with 3+ years of experience, proficiency in Verilog/SystemVerilog, and familiarity with ASIC methodologies. This is a hybrid position offering various health benefits and paid time-off.
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