RTL Design Engineer
Micron Technology, Boise, ID, United States
Job Summary
Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from specification through RTL implementation with a strong emphasis on power-efficient, implementation-aware building. The role involves hands‑on work with synthesis and timing/power analysis tools to create power, performance, and area trade‑offs, collaborating with cross‑functional teams to enhance the quality of advanced memory products.
Responsibilities
Develop and implement RTL for DRAM digital and mixed‑signal blocks using RTL‑to‑GDS flows.
Design power‑ and area‑efficient RTL with a focus on reducing switching activity, clock power, and leakage.
Perform front‑end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing quality of results.
Complete RTL‑ and gate‑level power and timing evaluations to identify and resolve PPA bottlenecks.
Collaborate with verification, synthesis, and physical design teams to achieve timing closure and design targets.
Minimum Qualifications
Master’s degree in Electrical Engineering with 3+ years of experience, or Bachelor’s degree with 4+ years of pre‑silicon RTL design experience.
Experience developing RTL for complex digital IP from specification through implementation handoff.
Hands‑on experience with ASIC low‑power methodologies, including UPF‑based power intent and CDC/RDC analysis.
Strong understanding of ASIC front‑end flows, including RTL design, synthesis, and static timing analysis.
Proficiency in Verilog/SystemVerilog and industry‑standard simulation tools.
Preferred Qualifications
Hands‑on experience with RTL and gate‑level power analysis using tools such as Design Compiler and PrimeTime.
Understanding of low‑power design techniques such as clock gating, power gating, and multi‑voltage designs.
Experience collaborating across RTL, verification, synthesis/STA, and physical design teams.
Familiarity with CMOS digital and mixed‑signal circuit concepts and their system‑level trade‑offs.
Experience with memory or high‑performance digital build is preferred.
Benefits
Micron offers comprehensive medical, dental, and vision plans, income protection, paid family leave, a robust paid time‑off program, and paid holidays.
Equal Opportunity Employer
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.
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Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from specification through RTL implementation with a strong emphasis on power-efficient, implementation-aware building. The role involves hands‑on work with synthesis and timing/power analysis tools to create power, performance, and area trade‑offs, collaborating with cross‑functional teams to enhance the quality of advanced memory products.
Responsibilities
Develop and implement RTL for DRAM digital and mixed‑signal blocks using RTL‑to‑GDS flows.
Design power‑ and area‑efficient RTL with a focus on reducing switching activity, clock power, and leakage.
Perform front‑end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing quality of results.
Complete RTL‑ and gate‑level power and timing evaluations to identify and resolve PPA bottlenecks.
Collaborate with verification, synthesis, and physical design teams to achieve timing closure and design targets.
Minimum Qualifications
Master’s degree in Electrical Engineering with 3+ years of experience, or Bachelor’s degree with 4+ years of pre‑silicon RTL design experience.
Experience developing RTL for complex digital IP from specification through implementation handoff.
Hands‑on experience with ASIC low‑power methodologies, including UPF‑based power intent and CDC/RDC analysis.
Strong understanding of ASIC front‑end flows, including RTL design, synthesis, and static timing analysis.
Proficiency in Verilog/SystemVerilog and industry‑standard simulation tools.
Preferred Qualifications
Hands‑on experience with RTL and gate‑level power analysis using tools such as Design Compiler and PrimeTime.
Understanding of low‑power design techniques such as clock gating, power gating, and multi‑voltage designs.
Experience collaborating across RTL, verification, synthesis/STA, and physical design teams.
Familiarity with CMOS digital and mixed‑signal circuit concepts and their system‑level trade‑offs.
Experience with memory or high‑performance digital build is preferred.
Benefits
Micron offers comprehensive medical, dental, and vision plans, income protection, paid family leave, a robust paid time‑off program, and paid holidays.
Equal Opportunity Employer
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.
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