Design Engineer
Aditi Consulting, Sunnyvale, CA, United States
Payrate
$117.00 - $120.00/hr
Summary
We are seeking an experienced engineer to perform power analysis and optimizations in ASIC for AR/VR products. The role involves working with Machine Learning technologies using primary languages such as Python, Tcl, and SystemVerilog.
Responsibilities
Perform PPA optimization with Fusion compiler.
Conduct RTL and netlist level power analysis.
Execute post‑processing and scripting on report log files for format conversion, data analysis, and information extraction.
Setup, run, debug, and analyze reports of ASIC flows including Synthesis, PD, Power, and Timing.
Implement some blocks at RTL and UPF.
Document and communicate clearly.
Qualifications
10 years of experience as an ASIC Power Engineer, or CAD Engineer/Physical Design Engineer.
Experience with power estimation tools and synthesis, and some physical design.
Knowledge of power trade‑offs in design and back‑end implementation.
Hands‑on experience in scripting and data analysis.
BS in Electrical Engineering/Computer Science or equivalent experience.
Desired Skills
Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
Proficiency in Python, Perl (or similar) scripting and data‑post‑processing tools.
Competency in Excel (or Matlab) for model fitting, data visualization, and analysis.
Experience in low‑power design, tools, and methodologies including power intent UPF specifications.
Silicon power characterization.
Power profiling experience at IP/SoC level.
Pay Transparency
The typical base pay for this role across the U.S. is $117.00 - $120.00 per hour. Non‑exempt positions are eligible for overtime at a rate of 1.5 times the base hourly rate for all hours worked in excess of 40 in a work week, or as required by state or local law. Final offer amounts, within the base pay set forth above, are determined by factors including your relevant skills, education and experience. Full‑time employees are eligible to select from different benefits packages. Packages may include medical, dental, and vision benefits, health savings accounts with qualified medical plan enrollment, 10 paid days off, 3 days paid bereavement leave, 401(k) plan participation with employer match, life and disability insurance, commuter benefits, dependent care flexible spending account, accident insurance, critical illness insurance, hospital indemnity insurance, accommodations and reimbursement for work travel, and discretionary performance or recognition bonus. Sick leave and mobile phone reimbursement provided based on state or local law.
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$117.00 - $120.00/hr
Summary
We are seeking an experienced engineer to perform power analysis and optimizations in ASIC for AR/VR products. The role involves working with Machine Learning technologies using primary languages such as Python, Tcl, and SystemVerilog.
Responsibilities
Perform PPA optimization with Fusion compiler.
Conduct RTL and netlist level power analysis.
Execute post‑processing and scripting on report log files for format conversion, data analysis, and information extraction.
Setup, run, debug, and analyze reports of ASIC flows including Synthesis, PD, Power, and Timing.
Implement some blocks at RTL and UPF.
Document and communicate clearly.
Qualifications
10 years of experience as an ASIC Power Engineer, or CAD Engineer/Physical Design Engineer.
Experience with power estimation tools and synthesis, and some physical design.
Knowledge of power trade‑offs in design and back‑end implementation.
Hands‑on experience in scripting and data analysis.
BS in Electrical Engineering/Computer Science or equivalent experience.
Desired Skills
Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
Proficiency in Python, Perl (or similar) scripting and data‑post‑processing tools.
Competency in Excel (or Matlab) for model fitting, data visualization, and analysis.
Experience in low‑power design, tools, and methodologies including power intent UPF specifications.
Silicon power characterization.
Power profiling experience at IP/SoC level.
Pay Transparency
The typical base pay for this role across the U.S. is $117.00 - $120.00 per hour. Non‑exempt positions are eligible for overtime at a rate of 1.5 times the base hourly rate for all hours worked in excess of 40 in a work week, or as required by state or local law. Final offer amounts, within the base pay set forth above, are determined by factors including your relevant skills, education and experience. Full‑time employees are eligible to select from different benefits packages. Packages may include medical, dental, and vision benefits, health savings accounts with qualified medical plan enrollment, 10 paid days off, 3 days paid bereavement leave, 401(k) plan participation with employer match, life and disability insurance, commuter benefits, dependent care flexible spending account, accident insurance, critical illness insurance, hospital indemnity insurance, accommodations and reimbursement for work travel, and discretionary performance or recognition bonus. Sick leave and mobile phone reimbursement provided based on state or local law.
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