PLL Design Engineer
Apple Inc., Austin, TX, United States
Description
In this role, you will leverage your expertise to develop cutting‑edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
Minimum Qualifications
BSEE with 0 years of relevant experience
Preferred Qualifications
Technical Expertise: Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional‑N, SSC, spur and jitter cancellation techniques, etc.
Good knowledge of band gaps, bias circuits, op‑amps, LDOs, feedback and compensation techniques.
Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
Simulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus.
Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem‑solving.
Innovation and Learning: A history of innovation and self‑directed learning, with demonstrated leadership skills and a growth mindset.
Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry‑standard design tools.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
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In this role, you will leverage your expertise to develop cutting‑edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
Minimum Qualifications
BSEE with 0 years of relevant experience
Preferred Qualifications
Technical Expertise: Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional‑N, SSC, spur and jitter cancellation techniques, etc.
Good knowledge of band gaps, bias circuits, op‑amps, LDOs, feedback and compensation techniques.
Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
Simulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus.
Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem‑solving.
Innovation and Learning: A history of innovation and self‑directed learning, with demonstrated leadership skills and a growth mindset.
Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry‑standard design tools.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
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