Analog Design Engineer for PLL/Adaptive Clocking
AMD, San Diego, CA, United States
THE ROLE AMD is searching for an experienced Circuit Design Engineer to join the fast‑growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering AMD products.
THE PERSON Solid knowledge of Mixed Signal Circuit Design in FinFET technology, specifically in PLLs and associated subblocks including VCO, adaptive clocking charge‑pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high‑speed buffers etc.
Solid knowledge of industry standard tools and practices for analog circuit design.
Good knowledge in physical design, STA, methodology scripts (Tcl), and familiarity with Perl and Python.
Quality‑oriented mindset.
Strong and effective communication skills and team spirit.
KEY RESPONSIBILITIES Design complex building blocks of a PLL, including architecture development and transistor‑level circuit design.
Run pre‑tapeout verification flows to confirm design meets performance, power, reliability, and timing requirements.
Work closely with mask design engineers to deliver the physical design and define production/bench‑level test plans with post‑silicon characterization groups for silicon evaluation to ensure interlocked and high‑quality execution.
Lead/mentor junior engineers.
PREFERRED EXPERIENCE Strong experience in the semiconductor industry.
Experience in FinFET & dual patterning nodes such as 16/14/10/7nm.
Hands‑on design experience in performance analog and hybrid PLLs, ADCs, DACs, VCO, LDO, bandgap, charge‑pump, op‑amps, interpolator circuits.
Experience with digital PLL techniques, TDC or DSP and control theory related to digital PLLs, dual charge‑pump PLL designs, fractional‑N PLLs, spread‑spectrum PLLs is a plus.
Proficiency with Cadence custom circuit design tools like ADE‑L and ADE‑XL and running Monte‑Carlo, noise, aging, EM and IR‑drop simulations and stability analysis; Helic/EMX is a plus.
Proficient with simulation tools such as Spectre, Hspice, AFS, MATLAB, System Verilog, and Python.
Capability to understand DRC and LVS results with verification tools (Calibre, ICV, or similar).
Proficiency in scripting languages like Perl, Python, MATLAB is a plus.
Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy.
Possess strong analytical/problem‑solving skills and pronounced attention to detail.
Must be a self‑starter, independent, and able to drive tasks to completion.
ACADEMIC CREDENTIALS Master’s in Electrical Engineering or equivalent preferred.
LOCATIONS San Diego, CA
THIS ROLE IS NOT ELIGIBLE FOR VISA SPONSORSHIP AMD does not sponsor visas for this position.
AMD benefits at a glance. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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THE PERSON Solid knowledge of Mixed Signal Circuit Design in FinFET technology, specifically in PLLs and associated subblocks including VCO, adaptive clocking charge‑pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high‑speed buffers etc.
Solid knowledge of industry standard tools and practices for analog circuit design.
Good knowledge in physical design, STA, methodology scripts (Tcl), and familiarity with Perl and Python.
Quality‑oriented mindset.
Strong and effective communication skills and team spirit.
KEY RESPONSIBILITIES Design complex building blocks of a PLL, including architecture development and transistor‑level circuit design.
Run pre‑tapeout verification flows to confirm design meets performance, power, reliability, and timing requirements.
Work closely with mask design engineers to deliver the physical design and define production/bench‑level test plans with post‑silicon characterization groups for silicon evaluation to ensure interlocked and high‑quality execution.
Lead/mentor junior engineers.
PREFERRED EXPERIENCE Strong experience in the semiconductor industry.
Experience in FinFET & dual patterning nodes such as 16/14/10/7nm.
Hands‑on design experience in performance analog and hybrid PLLs, ADCs, DACs, VCO, LDO, bandgap, charge‑pump, op‑amps, interpolator circuits.
Experience with digital PLL techniques, TDC or DSP and control theory related to digital PLLs, dual charge‑pump PLL designs, fractional‑N PLLs, spread‑spectrum PLLs is a plus.
Proficiency with Cadence custom circuit design tools like ADE‑L and ADE‑XL and running Monte‑Carlo, noise, aging, EM and IR‑drop simulations and stability analysis; Helic/EMX is a plus.
Proficient with simulation tools such as Spectre, Hspice, AFS, MATLAB, System Verilog, and Python.
Capability to understand DRC and LVS results with verification tools (Calibre, ICV, or similar).
Proficiency in scripting languages like Perl, Python, MATLAB is a plus.
Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy.
Possess strong analytical/problem‑solving skills and pronounced attention to detail.
Must be a self‑starter, independent, and able to drive tasks to completion.
ACADEMIC CREDENTIALS Master’s in Electrical Engineering or equivalent preferred.
LOCATIONS San Diego, CA
THIS ROLE IS NOT ELIGIBLE FOR VISA SPONSORSHIP AMD does not sponsor visas for this position.
AMD benefits at a glance. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
#J-18808-Ljbffr