Senior DFT Design Engineer III Scan/ATPG MBIST JTAG On-Site

A leading global electronics firm is looking for a Design For Test Engineer III in San Jose, CA. You will handle DFT implementation for advanced networking chips, along with responsibilities including RTL checks, pattern generation, and silicon debugging. Ideal candidates will have 5-7 years of experience in DFT, familiarity with multiple tools such as Mentor Tessent and VCS, and a degree in Microelectronics or Electronics. Attractive benefits package including medical insurance, 401k matching, and tuition reimbursement is offered.
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