Senior ASIC Design Verification Engineer (SV/UVM)

A global technology company seeking a Design Verification Engineer with at least 8 years of experience in ASIC. Responsibilities include working on SV/UVM scale test benches, ensuring customer satisfaction, and reporting on progress. A Bachelor's degree in electrical or computer engineering is required, with opportunities to travel to client sites. This role is fully onsite in San Jose, CA, and supports a leading semiconductor design service within a collaborative environment.
#J-18808-Ljbffr