Timing Design Engineer – ASIC STA & Sign-off

A leading technology company in Austin is seeking an ASIC STA Engineer to manage timing constraints throughout the SoC design process. Responsibilities include timing sign-off, developing STA flows, and collaboration with various teams to ensure timing closure. Ideal candidates must have a Bachelor's degree in Electrical Engineering, strong knowledge of ASIC design and timing methods, and 2+ years of related experience. Proficiency in STA tools and scripting languages is highly preferred, along with excellent communication skills.
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