Program Manager
Hcltech, Washington, District of Columbia, United States
Program Manager
To manage the program and ensure the integration and implementation of the program elements are as per agreed schedule| budget and quality so as to achieve the strategic intent of the program A SERDES analog design engineer with 8+ years of experience typically handles:
High-Speed Analog Circuit Design: Developing circuits for SERDES interfaces including transmitters (TX), receivers (RX), equalizers, samplers, phase interpolators (PI), deserializers, and bias/reference blocks
PLL and Clocking Systems: Designing analog and/or digital PLLs for frequency synthesis and SERDES applications, including sub-blocks like charge pumps, VCOs, and high-speed dividers
Verification and Simulation: Performing schematic to post-layout verification, functional and performance simulations across PVT corners, and co-simulations with digital RTL.
Post-Silicon Debug: Supporting bring-up and debugging of silicon, including IBIS modeling and timing generation.
Cross-Functional Collaboration: Working with RTL, PD, DV, and SoC teams to integrate PHYs and ensure performance targets are met.
Tools & Technologies:
EDA Tools: Cadence Virtuoso, Spectre, ADE-L/XL, Maestro, HSPICE, SimDE, and Fast Spice simulators.
Process Technologies: Experience across nodes like 180nm, 65nm, 40nm, 28nm, 16nm, 7nm, and even down to 3nm for advanced FinFET designs.
Scripting: Familiarity with Shell, Perl, Python for automating design and verification tasks.
Design Domains:
SERDES Protocols: PCIe Gen1Gen4, Ethernet (10G-BASEKR), UCIe, USB2, LPDDR5, DDR5, and PON protocol implementations.
Power Management: LDOs (Capless and Capped), Bandgap references, DC-DC converters, charge pumps, and temperature sensors.
Mixed-Signal Blocks: ADCs (SAR, Flash), DACs (Current Steering), comparators, operational amplifiers, and relaxation oscillators.
Key Responsibilities:
To ensure value creation in the engagement
To manage key Program Partners / Stakeholders interests for smooth integration and implementation of the program and achievement of its objectives.
To manage engagement profitability by managing various variables
To proactively engage with the client to understand the business engagements
To lead| manage| develop and engage the team
To proactively identify and mitigate risks & issues (including escalations) for delivery of the program
Skill Requirements null Other Requirements null Maximum Salary (US): 223000 Minimum Salary (US): 169000
To manage the program and ensure the integration and implementation of the program elements are as per agreed schedule| budget and quality so as to achieve the strategic intent of the program A SERDES analog design engineer with 8+ years of experience typically handles:
High-Speed Analog Circuit Design: Developing circuits for SERDES interfaces including transmitters (TX), receivers (RX), equalizers, samplers, phase interpolators (PI), deserializers, and bias/reference blocks
PLL and Clocking Systems: Designing analog and/or digital PLLs for frequency synthesis and SERDES applications, including sub-blocks like charge pumps, VCOs, and high-speed dividers
Verification and Simulation: Performing schematic to post-layout verification, functional and performance simulations across PVT corners, and co-simulations with digital RTL.
Post-Silicon Debug: Supporting bring-up and debugging of silicon, including IBIS modeling and timing generation.
Cross-Functional Collaboration: Working with RTL, PD, DV, and SoC teams to integrate PHYs and ensure performance targets are met.
Tools & Technologies:
EDA Tools: Cadence Virtuoso, Spectre, ADE-L/XL, Maestro, HSPICE, SimDE, and Fast Spice simulators.
Process Technologies: Experience across nodes like 180nm, 65nm, 40nm, 28nm, 16nm, 7nm, and even down to 3nm for advanced FinFET designs.
Scripting: Familiarity with Shell, Perl, Python for automating design and verification tasks.
Design Domains:
SERDES Protocols: PCIe Gen1Gen4, Ethernet (10G-BASEKR), UCIe, USB2, LPDDR5, DDR5, and PON protocol implementations.
Power Management: LDOs (Capless and Capped), Bandgap references, DC-DC converters, charge pumps, and temperature sensors.
Mixed-Signal Blocks: ADCs (SAR, Flash), DACs (Current Steering), comparators, operational amplifiers, and relaxation oscillators.
Key Responsibilities:
To ensure value creation in the engagement
To manage key Program Partners / Stakeholders interests for smooth integration and implementation of the program and achievement of its objectives.
To manage engagement profitability by managing various variables
To proactively engage with the client to understand the business engagements
To lead| manage| develop and engage the team
To proactively identify and mitigate risks & issues (including escalations) for delivery of the program
Skill Requirements null Other Requirements null Maximum Salary (US): 223000 Minimum Salary (US): 169000