SerDes Architect and Design Engineer
Chelsea Search Group, Los Angeles, CA, United States
SerDes Architect and Design Engineer
Responsibilities
Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
Define architecture, specifications, and circuit topologies for next-generation SerDes
Design high-performance analog/mixed-signal circuits in advanced node technologies
Develop and oversee the design of critical blocks including RX/TX equalization (CTLE, DFE), high-speed PLLs, phase interpolators, DLLs, TDCs
Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve power, performance, and area
Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
Oversee development of system‑level modeling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog‑A) to analyze link budgets, equalization strategies, and jitter budgeting
Oversee analysis of signal integrity and power integrity to achieve system‑defined targets
Required Skills & Experience
Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
Experience in lab bring‑up, characterization, and debugging designs that reach out production
Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
Prior experience in cross‑functional interaction to deliver IP and ensuring seamless integration in SOCs
Proven record of taking high-speed SerDes design to tape‑out and volume production
Strong communication and documentation skills
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Responsibilities
Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
Define architecture, specifications, and circuit topologies for next-generation SerDes
Design high-performance analog/mixed-signal circuits in advanced node technologies
Develop and oversee the design of critical blocks including RX/TX equalization (CTLE, DFE), high-speed PLLs, phase interpolators, DLLs, TDCs
Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve power, performance, and area
Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
Oversee development of system‑level modeling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog‑A) to analyze link budgets, equalization strategies, and jitter budgeting
Oversee analysis of signal integrity and power integrity to achieve system‑defined targets
Required Skills & Experience
Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
Experience in lab bring‑up, characterization, and debugging designs that reach out production
Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
Prior experience in cross‑functional interaction to deliver IP and ensuring seamless integration in SOCs
Proven record of taking high-speed SerDes design to tape‑out and volume production
Strong communication and documentation skills
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