Physical Design Engineer II (Full Time) - United States
Cisco Systems, Inc., Austin, TX, United States
Responsibilities
As a Physical Design Engineer with Acacia, you will focus on the technical execution of high‑performance ASIC designs. Working as an individual contributor, you will own the RTL‑to‑GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia’s networking platforms meet rigorous power, performance, and area targets.
Implement end‑to‑end RTL‑to‑GDSII implementation for advanced nodes (sub‑7nm)
Perform floor planning, place and route, and clock/power distribution
Conduct static timing analysis (STA) and drive timing closure for multi‑mode/multi‑corner designs
Manage the physical design of assigned blocks, ensuring quality and consistency to project timelines
Collaborate with the Physical Design team to debug and resolve complex physical implementation issues
Implement ECO strategies and support sign‑off processes
Contribute to the refinement of design methodologies and standard processes within the engineering team
Document and track progress for assigned project achievements
Minimum Qualifications
Completion within the past 3 years, or current enrollment with expected completion within 12 months, a Bachelors + 2 years of relevant experience or Masters + 0 years of relevant experience. Relevant fields include Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
Hands‑on experience in ASIC physical design and implementation.
Working knowledge with hierarchical floorplanning, clock and power distribution, global signal and I/O planning, along with physical convergence, timing closure, and hierarchical design methodology.
Understanding power integrity and EMIR analysis.
Preferred Qualifications
Experience with scripting using languages such as TCL, Perl, Python, etc.
Place & Route experience using tools such as Cadence Innovus or Synopsys ICC2.
Experience with formal equivalence check, timing closure, EMIR, physical verification DRC/LVS.
Experience with block level EMIR closure.
Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre.
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As a Physical Design Engineer with Acacia, you will focus on the technical execution of high‑performance ASIC designs. Working as an individual contributor, you will own the RTL‑to‑GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia’s networking platforms meet rigorous power, performance, and area targets.
Implement end‑to‑end RTL‑to‑GDSII implementation for advanced nodes (sub‑7nm)
Perform floor planning, place and route, and clock/power distribution
Conduct static timing analysis (STA) and drive timing closure for multi‑mode/multi‑corner designs
Manage the physical design of assigned blocks, ensuring quality and consistency to project timelines
Collaborate with the Physical Design team to debug and resolve complex physical implementation issues
Implement ECO strategies and support sign‑off processes
Contribute to the refinement of design methodologies and standard processes within the engineering team
Document and track progress for assigned project achievements
Minimum Qualifications
Completion within the past 3 years, or current enrollment with expected completion within 12 months, a Bachelors + 2 years of relevant experience or Masters + 0 years of relevant experience. Relevant fields include Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
Hands‑on experience in ASIC physical design and implementation.
Working knowledge with hierarchical floorplanning, clock and power distribution, global signal and I/O planning, along with physical convergence, timing closure, and hierarchical design methodology.
Understanding power integrity and EMIR analysis.
Preferred Qualifications
Experience with scripting using languages such as TCL, Perl, Python, etc.
Place & Route experience using tools such as Cadence Innovus or Synopsys ICC2.
Experience with formal equivalence check, timing closure, EMIR, physical verification DRC/LVS.
Experience with block level EMIR closure.
Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre.
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