Testing Engineer IV - PCIe
Astreya Inc., Austin, TX, United States
Testing Engineer IV - PCIe page is loaded## Testing Engineer IV - PCIelocations:
Sunnyvale, CA:
San Jose, CA:
Austin, TX:
Portland, ORtime type:
Full timeposted on:
Posted Todayjob requisition id:
R0014943**About the Role:**We are seeking an experienced and highly technical Hardware Verification & Validation Engineer to drive the end-to-end testing of our cutting-edge ASIC designs. In this dynamic role, you will bridge the gap between pre-silicon verification and post-silicon lab validation. You will architect robust UVM testbenches for next-generation PCIe interfaces and lead hands-on silicon bring-up in the lab. If you have deep expertise in high-speed IO and thrive in cross-functional debugging environments, we want you on our team.**Key Responsibilities: Pre-Silicon Verification (PCIe Focus)*** **Verification Planning:** Architect and execute comprehensive verification plans for PCIe Switch, Root Complex, and Endpoint configurations.* **Testbench Development:** Build and scale UVM-based environments from scratch to rigorously test complex PCIe protocol behaviors, including LTSSM transitions and link training.* **Performance Verification:** Leverage advanced simulation and emulation platforms to ensure high-performance throughput and strict protocol compliance across PCIe Gen 4, Gen 5, and Gen 6.* **Cross-Functional Debug:** Partner closely with RTL design, architecture, and software teams to root-cause and rapidly resolve functional failures.**Key Responsibilities: Post-Silicon Validation & Labs*** **Silicon Bring-up:** Lead the initial power-on, initialization, and functional testing of high-speed IO interfaces, with a specific focus on PCIe Gen 5/6.* **Lab Validation:** Utilize high-end laboratory equipment—including oscilloscopes, Bit Error Rate Testers (BERTs), and protocol analyzers—to validate electrical and functional correctness.* **Failure Analysis:** Reproduce complex silicon bugs in a physical lab environment and perform deep root-cause analysis to remediate hardware issues.* **Validation Automation:** Develop and maintain robust automation frameworks using Python or C++ to streamline large-scale validation workflows and data collection.**Qualifications*** **Education:** BS or MS in Electrical Engineering, Computer Engineering, or a closely related technical field.* **Experience:** 6–8+ years of hands-on, proven experience in ASIC development, pre-silicon verification, or post-silicon system validation.* **Protocol Expertise:** In-depth, structural knowledge of all PCIe protocol layers (Physical, Data Link, and Transaction).* **Programming Skills:** Strong coding proficiency in Python, C/C++, and SystemVerilog.* **Tools & Environments:** Solid familiarity with Linux environments and standard hardware debugging tools (e.g., JTAG, GDB, Trace32).**Salary Range**$98,040.00 - $154,800.00 USD (Salary)* *Please note that the salary information provided herein is base pay only (gross); it does not include other forms of compensation which may or may not apply to this specific position, namely, performance-based bonuses, benefits-related payments, or other general incentives - none of which are guaranteed, may be subject to specific eligibility requirements, and are wholly within the discretion of Astreya to remit.** *Further, the salary information noted above is a range that consists of a minimum and maximum rate of pay for this specific position. Where an applicant or employee is placed on this range will depend and be contingent on objective, documented work-related considerations like education, experience, certifications, licenses, preferred qualifications, among other factors.***Astreya** **offers comprehensive** **b****enefits to all Regular, Full-Time Employees,** **including:*** Medical provided through UHC (PPO, HSA, Surest options) / Medical provided through Kaiser (HMO option only) for California employees only* Dental provided through UHC* Nationwide Vision provided by UHC* Flexible Spending Account for Health & Dependent Care* Pre-Tax Account for Commuter Benefit/Parking & Transit (location-specific)* Continuing Education and Professional Development via various integrated platforms, e.g. Udemy and Coursera* Corporate Wellness Program provided by Goomi Group* Employee Assistance Program* Wellness Days
401k Plan* Basic and Supplemental Life Insurance* Short Term & Long Term Disability* Critical Illness, Critical Hospital, and Voluntary Accident Insurance* Tuition Reimbursement (available 6 months after start date, capped)* Paid Time Off (accrued and prorated, maximum of 120 hours annually)* Paid Holidays* Any other statutory leaves, paid time, or other ancillary benefits required under state and federal law
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Sunnyvale, CA:
San Jose, CA:
Austin, TX:
Portland, ORtime type:
Full timeposted on:
Posted Todayjob requisition id:
R0014943**About the Role:**We are seeking an experienced and highly technical Hardware Verification & Validation Engineer to drive the end-to-end testing of our cutting-edge ASIC designs. In this dynamic role, you will bridge the gap between pre-silicon verification and post-silicon lab validation. You will architect robust UVM testbenches for next-generation PCIe interfaces and lead hands-on silicon bring-up in the lab. If you have deep expertise in high-speed IO and thrive in cross-functional debugging environments, we want you on our team.**Key Responsibilities: Pre-Silicon Verification (PCIe Focus)*** **Verification Planning:** Architect and execute comprehensive verification plans for PCIe Switch, Root Complex, and Endpoint configurations.* **Testbench Development:** Build and scale UVM-based environments from scratch to rigorously test complex PCIe protocol behaviors, including LTSSM transitions and link training.* **Performance Verification:** Leverage advanced simulation and emulation platforms to ensure high-performance throughput and strict protocol compliance across PCIe Gen 4, Gen 5, and Gen 6.* **Cross-Functional Debug:** Partner closely with RTL design, architecture, and software teams to root-cause and rapidly resolve functional failures.**Key Responsibilities: Post-Silicon Validation & Labs*** **Silicon Bring-up:** Lead the initial power-on, initialization, and functional testing of high-speed IO interfaces, with a specific focus on PCIe Gen 5/6.* **Lab Validation:** Utilize high-end laboratory equipment—including oscilloscopes, Bit Error Rate Testers (BERTs), and protocol analyzers—to validate electrical and functional correctness.* **Failure Analysis:** Reproduce complex silicon bugs in a physical lab environment and perform deep root-cause analysis to remediate hardware issues.* **Validation Automation:** Develop and maintain robust automation frameworks using Python or C++ to streamline large-scale validation workflows and data collection.**Qualifications*** **Education:** BS or MS in Electrical Engineering, Computer Engineering, or a closely related technical field.* **Experience:** 6–8+ years of hands-on, proven experience in ASIC development, pre-silicon verification, or post-silicon system validation.* **Protocol Expertise:** In-depth, structural knowledge of all PCIe protocol layers (Physical, Data Link, and Transaction).* **Programming Skills:** Strong coding proficiency in Python, C/C++, and SystemVerilog.* **Tools & Environments:** Solid familiarity with Linux environments and standard hardware debugging tools (e.g., JTAG, GDB, Trace32).**Salary Range**$98,040.00 - $154,800.00 USD (Salary)* *Please note that the salary information provided herein is base pay only (gross); it does not include other forms of compensation which may or may not apply to this specific position, namely, performance-based bonuses, benefits-related payments, or other general incentives - none of which are guaranteed, may be subject to specific eligibility requirements, and are wholly within the discretion of Astreya to remit.** *Further, the salary information noted above is a range that consists of a minimum and maximum rate of pay for this specific position. Where an applicant or employee is placed on this range will depend and be contingent on objective, documented work-related considerations like education, experience, certifications, licenses, preferred qualifications, among other factors.***Astreya** **offers comprehensive** **b****enefits to all Regular, Full-Time Employees,** **including:*** Medical provided through UHC (PPO, HSA, Surest options) / Medical provided through Kaiser (HMO option only) for California employees only* Dental provided through UHC* Nationwide Vision provided by UHC* Flexible Spending Account for Health & Dependent Care* Pre-Tax Account for Commuter Benefit/Parking & Transit (location-specific)* Continuing Education and Professional Development via various integrated platforms, e.g. Udemy and Coursera* Corporate Wellness Program provided by Goomi Group* Employee Assistance Program* Wellness Days
401k Plan* Basic and Supplemental Life Insurance* Short Term & Long Term Disability* Critical Illness, Critical Hospital, and Voluntary Accident Insurance* Tuition Reimbursement (available 6 months after start date, capped)* Paid Time Off (accrued and prorated, maximum of 120 hours annually)* Paid Holidays* Any other statutory leaves, paid time, or other ancillary benefits required under state and federal law
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