Staff IP Design Engineer: High-Speed FPGA & Connectivity

Lattice is looking for a passionate Staff IP Design Engineer based in Idaho, USA, to build Connectivity IP portfolios for Lattice FPGA. The ideal candidate will possess a strong background in high-speed SERDES, programming, and FPGA design with at least 8 years of experience. This position emphasizes innovation and problem-solving in a dynamic team environment. Competitive candidates will be self-motivated and capable of executing under uncertainties while working collaboratively with diverse engineers.
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