Signal Integrity/Power Integrity Engineer
HCLTech, Redmond, WA, United States
Job Summary
Looking for a Senior SI/PI Engineer with deep expertise in high‑speed serial interfaces, DDR memory simulations, PDN design, and advanced EM tools.
Key Responsibilities
Perform Signal Integrity (SI) and Power Integrity (PI) analysis for high‑speed digital designs.
Apply strong fundamentals of SI/PI concepts, including transmission line theory and S‑parameter modeling.
Simulate memory interfaces (DDR4 / LPDDR4) at board and package levels using frequency‑domain and time‑domain methods.
Simulate high‑speed serial interfaces at board and package levels, including PCIe Gen3/4, SATA Gen3, USB 3.0/3.1, and display interfaces.
Analyze and optimize Power Delivery Networks (PDN), including impedance profiling, IR drop analysis, and time‑domain analysis.
Extract PDN models for package and PCB power rails and perform decoupling capacitor optimization and loop inductance analysis.
Collaborate with cross‑functional teams to resolve SI/PI issues and improve overall design quality.
Technical Skills Required
6–8 years of strong experience in Signal Integrity and Power Integrity.
Deep understanding of S‑parameters and modeling for single‑ended and differential interfaces.
Strong knowledge of PDN design, impedance analysis, IR drop, and time‑domain behavior.
Experience in simulating (FD/TD) memory interfaces for Board and Package (DDR4/LPDDR4).
Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package (PCIe Gen3/4, SATA Gen3, USB3/3.1 and Display Interfaces).
Strong knowledge in simulation tools such as Hspice, Sigrity (2.5D and 3D-EM), ADS and other tools like Ansys SIwave, HFSS 3D, Cadence PowerSI & PowerDC.
Soft Skills
Excellent verbal and written communication with strong attention to detail.
Strong problem‑solving, debugging, and analytical skills.
Ability to quickly learn and adapt in a fast‑paced, dynamic environment.
Effective team player with the ability to work independently when needed.
Capability to understand and follow technical documentation, specs, emails, and training materials accurately.
Profile Description
We are looking for a highly skilled Signal & Power Integrity (SI/PI) Engineer with strong fundamentals and hands‑on experience in high‑speed design analysis. The ideal candidate will work closely with design teams to ensure robust signal and power integrity across complex board and package designs.
Benefits
Compensation and Benefits: A candidate’s pay within the range will depend on their work location, skills, experience, education, and other factors permitted by law. This role may also be eligible for performance‑based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need‑based leave with no designated number of leave days per year); and 10 paid holidays per year.
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Looking for a Senior SI/PI Engineer with deep expertise in high‑speed serial interfaces, DDR memory simulations, PDN design, and advanced EM tools.
Key Responsibilities
Perform Signal Integrity (SI) and Power Integrity (PI) analysis for high‑speed digital designs.
Apply strong fundamentals of SI/PI concepts, including transmission line theory and S‑parameter modeling.
Simulate memory interfaces (DDR4 / LPDDR4) at board and package levels using frequency‑domain and time‑domain methods.
Simulate high‑speed serial interfaces at board and package levels, including PCIe Gen3/4, SATA Gen3, USB 3.0/3.1, and display interfaces.
Analyze and optimize Power Delivery Networks (PDN), including impedance profiling, IR drop analysis, and time‑domain analysis.
Extract PDN models for package and PCB power rails and perform decoupling capacitor optimization and loop inductance analysis.
Collaborate with cross‑functional teams to resolve SI/PI issues and improve overall design quality.
Technical Skills Required
6–8 years of strong experience in Signal Integrity and Power Integrity.
Deep understanding of S‑parameters and modeling for single‑ended and differential interfaces.
Strong knowledge of PDN design, impedance analysis, IR drop, and time‑domain behavior.
Experience in simulating (FD/TD) memory interfaces for Board and Package (DDR4/LPDDR4).
Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package (PCIe Gen3/4, SATA Gen3, USB3/3.1 and Display Interfaces).
Strong knowledge in simulation tools such as Hspice, Sigrity (2.5D and 3D-EM), ADS and other tools like Ansys SIwave, HFSS 3D, Cadence PowerSI & PowerDC.
Soft Skills
Excellent verbal and written communication with strong attention to detail.
Strong problem‑solving, debugging, and analytical skills.
Ability to quickly learn and adapt in a fast‑paced, dynamic environment.
Effective team player with the ability to work independently when needed.
Capability to understand and follow technical documentation, specs, emails, and training materials accurately.
Profile Description
We are looking for a highly skilled Signal & Power Integrity (SI/PI) Engineer with strong fundamentals and hands‑on experience in high‑speed design analysis. The ideal candidate will work closely with design teams to ensure robust signal and power integrity across complex board and package designs.
Benefits
Compensation and Benefits: A candidate’s pay within the range will depend on their work location, skills, experience, education, and other factors permitted by law. This role may also be eligible for performance‑based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need‑based leave with no designated number of leave days per year); and 10 paid holidays per year.
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