Senior RTL Design Architect – Mixed-Signal IPs (UCIe/DDR)

A leading semiconductor company is seeking an experienced ASIC Digital Design engineer in Sunnyvale, California. The role involves leading RTL design and implementation for high-performance mixed signal IPs, including UCIe and DDR interfaces. The ideal candidate has over 8 years of RTL design experience, strong expertise in Verilog/SystemVerilog, and a passion for innovation. You will work in a dynamic team environment that fosters collaboration and technical excellence, while also mentoring junior engineers. This position offers a comprehensive range of health, wellness, and financial benefits.
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