High-Level Synthesis (HLS) Engineer

About Altera

Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge.
About the Role

Altera is at the forefront of programmable logic and hardware acceleration. As a member of the High‑Level Synthesis (HLS) research and engineering team, you will work on both production compiler systems and forward‑looking research.
Key Responsibilities

Design and develop next‑generation compiler infrastructure for HLS
Invent and implement novel compiler passes, optimizations, and code transformations for hardware synthesis
Explore advanced compilation techniques for AI/ML workloads, including graph‑level and system‑level optimizations
Improve end‑to‑end compilation flow from C/C++ (and beyond) to RTL, focusing on performance, power, and area efficiency
Prototype and evaluate new ideas in collaboration with research and product teams
Contribute to publications, patents, and internal technical innovations
Work closely with hardware architects and domain experts to co‑design future acceleration platforms
What We Offer

A collaborative environment where research ideas turn into shipped products
Competitive compensation and benefits
Opportunities for career growth in both research and engineering tracks
A culture that values innovation, ownership, and technical excellence
Salary

$133.2K - $192.8K USD (BayArea, California only; actual salary may vary based on a number of factors).
Qualifications

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or related field, with 3+ years of experience
Strong foundation in one or more of: compiler design (e.g., optimization, IR design, code generation); programming languages or systems; computer architecture or digital design
Proficiency in C/C++ or similar systems programming languages
Research experience in compilers, HLS, or hardware/software co‑design (preferred)
Familiarity with LLVM, MLIR, or similar compiler infrastructures (preferred)
Exposure to FPGA/ASIC design flows or hardware description languages (Verilog/VHDL) (preferred)
Background in optimizing AI/ML workloads or domain‑specific accelerators (preferred)
Publications in relevant conferences or demonstrated research impact (preferred)
Job Type

Regular
Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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