Integrated Circuit Layout Designer
Lockheed Martin, Goleta, CA, United States
Integrated Circuit Layout Designer – Readout Integrated Circuit (ROIC) Design Team
You will be the Integrated Circuit Layout Designer for the Readout Integrated Circuit (ROIC) design team at LockheedMartin’s SantaBarbara Focal plane business. Our team delivers world class ROICs that power next generation infrared and visible spectrum imagers for defense, science, and commercial markets.
What You Will Be Doing As the Integrated Circuit Layout Designer you will translate high performance analog and digital schematics into robust silicon layouts that meet sub‑micron, mixed‑signal VLSI specifications. Working side by side with circuit designers, verification engineers, and process experts, you will turn cutting‑edge ROIC concepts into manufacturable silicon blocks that enable ultra‑low noise, low‑power, high‑speed imaging.
Perform full custom physical layout of mixed‑signal CMOS transistor‑level designs, including ultra‑low noise front ends, low‑power ADCs, and multi‑GHz SERDES blocks.
Apply Design for Manufacturability (DFM) and Design for Test (DFT) techniques to satisfy tight area, thermal, and performance constraints.
Generate and maintain layout documentation, DRC/LVS reports, and tape‑out release packages.
Conduct parasitic extraction and post‑layout simulations to verify electrical performance against specifications.
Collaborate with circuit designers, verification engineers, and process engineers to resolve layout issues quickly and iterate efficiently.
Implement and enforce best‑practice guidelines in the team’s layout library.
Mentor junior technicians, fostering an inclusive, knowledge‑sharing culture.
Location Santa Barbara, California.
Clearance Required This position requires US citizenship and the ability to obtain a secret clearance.
Basic Qualifications
Bachelor’s degree or higher in a related discipline with 3+ years of experience in IC layout design, OR training and 5+ years of experience in IC layout design.
Experience with IC design in Cadence Virtuoso tool suite.
Desired Skills
Experience in custom CMOS integrated circuit transistor and standard cell layout.
Experience in Cadence Virtuoso Layout XL, GXL, MXL, and Siemens Calibre.
Benefits and Compensation Competitive annual base salary range: $97,100 - $171,235 (varies by state). Benefits include medical, dental, vision, life insurance, short‑term and long‑term disability, 401(k) match, flexible spending accounts, employee assistance program, education assistance, parental leave, paid time off, holidays, and other incentives.
Equal Opportunity Employer Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.
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What You Will Be Doing As the Integrated Circuit Layout Designer you will translate high performance analog and digital schematics into robust silicon layouts that meet sub‑micron, mixed‑signal VLSI specifications. Working side by side with circuit designers, verification engineers, and process experts, you will turn cutting‑edge ROIC concepts into manufacturable silicon blocks that enable ultra‑low noise, low‑power, high‑speed imaging.
Perform full custom physical layout of mixed‑signal CMOS transistor‑level designs, including ultra‑low noise front ends, low‑power ADCs, and multi‑GHz SERDES blocks.
Apply Design for Manufacturability (DFM) and Design for Test (DFT) techniques to satisfy tight area, thermal, and performance constraints.
Generate and maintain layout documentation, DRC/LVS reports, and tape‑out release packages.
Conduct parasitic extraction and post‑layout simulations to verify electrical performance against specifications.
Collaborate with circuit designers, verification engineers, and process engineers to resolve layout issues quickly and iterate efficiently.
Implement and enforce best‑practice guidelines in the team’s layout library.
Mentor junior technicians, fostering an inclusive, knowledge‑sharing culture.
Location Santa Barbara, California.
Clearance Required This position requires US citizenship and the ability to obtain a secret clearance.
Basic Qualifications
Bachelor’s degree or higher in a related discipline with 3+ years of experience in IC layout design, OR training and 5+ years of experience in IC layout design.
Experience with IC design in Cadence Virtuoso tool suite.
Desired Skills
Experience in custom CMOS integrated circuit transistor and standard cell layout.
Experience in Cadence Virtuoso Layout XL, GXL, MXL, and Siemens Calibre.
Benefits and Compensation Competitive annual base salary range: $97,100 - $171,235 (varies by state). Benefits include medical, dental, vision, life insurance, short‑term and long‑term disability, 401(k) match, flexible spending accounts, employee assistance program, education assistance, parental leave, paid time off, holidays, and other incentives.
Equal Opportunity Employer Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.
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