Senior SoC Performance Architect (Santa Clara)
Huntech USA LLC, Santa Clara, CA, United States
We are open to any locations within USA. The compensation will be adjusted based on the location.
As a SoC Performance Architect, you will create performance and power models for the fabric NoC /DRAM controller/IO blocks for server-class SoCs, correlate models against RTL behavior, prototype ideas and help productize performance/power features for future SoC designs.
Develop a SoC performance/power model for blocks such as interconnect NoCs, distributed system caches, memory controllers, IO controllers
Verify model correctness by writing unit-tests and debugging mismatches against expectations
Identify ideas for improving the SoC’s performance/power characteristics. Prototype the idea in the performance/power model and thoroughly characterize it
Work with architects and RTL developers to productize the improvements identified through detailed studies
Conduct RTL performance verification. This will involve creation of verification plans and directed tests / checkers
Minimum Skill sets:
MS in Computer Science/Computer Engineering/Electrical Engineer with 6 years of experience in CPU/SoC performance/power modeling, analysis/debug
Strong grasp of the computer architecture fundamentals especially in the areas of interconnects, traffic QoS, distributed caches, coherency flows, DRAM controller and IO (PCIe) flows
2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).
Proficient in C++ and Perl / Python
Exposure to performance analysis and debug
Ability to independently identify, troubleshoot and solve performance problems
Expertise in one or more of these functional areas:
Coherent fabrics based on the AMBA CHI / AXI protocol
Memory controller designs for LPDDR5, DDR5
IO controllers and fabric bridges for PCIe/CXL/CCIX
Strong background in building fast, accurate SoC/CPU performance models in C++
Exposure to testing and debugging performance issues in pre- and post-silicon environments and demonstrable experience in productizing features that improve performance/power characteristics of a design
As a SoC Performance Architect, you will create performance and power models for the fabric NoC /DRAM controller/IO blocks for server-class SoCs, correlate models against RTL behavior, prototype ideas and help productize performance/power features for future SoC designs.
Develop a SoC performance/power model for blocks such as interconnect NoCs, distributed system caches, memory controllers, IO controllers
Verify model correctness by writing unit-tests and debugging mismatches against expectations
Identify ideas for improving the SoC’s performance/power characteristics. Prototype the idea in the performance/power model and thoroughly characterize it
Work with architects and RTL developers to productize the improvements identified through detailed studies
Conduct RTL performance verification. This will involve creation of verification plans and directed tests / checkers
Minimum Skill sets:
MS in Computer Science/Computer Engineering/Electrical Engineer with 6 years of experience in CPU/SoC performance/power modeling, analysis/debug
Strong grasp of the computer architecture fundamentals especially in the areas of interconnects, traffic QoS, distributed caches, coherency flows, DRAM controller and IO (PCIe) flows
2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).
Proficient in C++ and Perl / Python
Exposure to performance analysis and debug
Ability to independently identify, troubleshoot and solve performance problems
Expertise in one or more of these functional areas:
Coherent fabrics based on the AMBA CHI / AXI protocol
Memory controller designs for LPDDR5, DDR5
IO controllers and fabric bridges for PCIe/CXL/CCIX
Strong background in building fast, accurate SoC/CPU performance models in C++
Exposure to testing and debugging performance issues in pre- and post-silicon environments and demonstrable experience in productizing features that improve performance/power characteristics of a design