Layout & Mask Design Engineer (DRAM/Memory)

A leading semiconductor firm is seeking a Layout Engineer in Boise, Idaho, to create block-level layouts and ensure compliance with physical design standards. The position requires experience with Cadence Virtuoso and familiarity with physical layout verification processes. Ideal candidates have strong teamwork and communication skills and will work closely with global teams on critical DRAM product designs. This full-time role offers a salary range of $54.00 to $92.00 per hour, plus benefits.
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