DRAM Layout Engineer: Memory & Analog Design

A leading semiconductor solutions company in Boise is seeking a Layout Engineer to develop and verify advanced semiconductor layouts. The role involves utilizing CAD tools and collaborating with global teams to ensure high-quality outputs. Candidates should hold a Bachelor’s degree in a relevant field and have familiarity with layout tools like Cadence Virtuoso VXL and Calibre. Preferred qualifications include experience in memory product layout and scripting with SKILL or Python.
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