Layout Engineer: DRAM & Memory Design

A leading semiconductor company in Boise, Idaho, is seeking a Layout Engineer to work on block-level designs that influence DRAM product quality. The role involves using Cadence Virtuoso for layout tasks including floorplanning, routing, and ensuring compliance with design rules. Ideal candidates should possess hands-on layout experience, familiarity with verification processes, and strong communication skills for collaboration across teams. Opportunities for professional growth and robust benefits are offered, including medical plans and paid time off.
#J-18808-Ljbffr