Senior RTL Design Engineer, Memory IO & DDR PHY

A technology firm is seeking a Senior RTL Engineer to join their DDR PHY design team in Austin, Texas. This role involves analyzing complex digital design problems, driving ASIC design flows, and collaborating with various teams. The ideal candidate will have over 10 years of experience in RTL design, especially with high-speed interfaces like DDR, and hold a Bachelor's or Master's degree in Electrical Engineering. Competitive benefits are offered, and the position is not eligible for visa sponsorship.
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