Senior Design Verification Engineer - QGOV
Qualcomm, San Diego, CA, United States
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering
General Summary
Role: Familiarity with RTL design in Verilog and SystemVerilog. Develop verification methodology, ensuring scalable and portable environment across simulation and emulation. Develop test plans to verify hardware building blocks, design macros and standard interfaces (PCIe, DDR, USB, I2C, SPI, etc). Own end-to-end DV tasks from coding test benches and test cases, write assertions, run simulations and achieve all coverage goals. Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches. Develop and maintain emulation environment to collect metrics related to emulation environment. Will need to be in San Diego full time, 5 days a week.
Security and citizenship requirements
Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Required Qualifications
5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture
5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows
Note: Relevant experience of 2-3+ years in any of the mentioned domain - Design/Verification/Implementation.
Preferred Qualifications
Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.
Strong SystemVerilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
Good understanding of chip-level functional model building
Good understanding of OOP concepts; Experience in HVL such as SystemVerilog, UVM/OVM & SystemC
Knowledge of Behavioral and Structural models and familiarity with simulation environments
Experience with make-based build flows and Xilinx Vivado tools
Experience with cm tools such as Git and Gerrit
Experience in formal / static verification methodologies is a plus
Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs
Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog
Experience with C/C++ DPI transactors and monitors
Develop and maintain emulation environment to collect metrics related to emulation environment
Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors
Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations
Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures
Experience with debugging tools such as JTAG and lab test equipment (logic analyzers, oscilloscopes, signal generators, etc.)
Experience with GLS, and scripting languages such as Perl, Python is a plus
Linux OS proficiency
The ideal candidate would be a self-starter with strong initiative, discipline, motivation, and a focus on quality.
The candidate must be a team player and be flexible and open to a variety of task assignments within the team.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
EEO and Benefits
Qualcomm is an equal opportunity employer. Qualcomm is committed to providing an accessible process for individuals with disabilities during the application/hiring process. For accommodations, please contact disability-accommodations@qualcomm.com. Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Pay range and Other Compensation & Benefits: $104,100.00 - $173,400.00
The pay range reflects a broad minimum to maximum for the location. Salary is one component of total compensation, which may include discretionary bonuses and RSU grants. Benefits details are discussed with your recruiter.
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General Summary
Role: Familiarity with RTL design in Verilog and SystemVerilog. Develop verification methodology, ensuring scalable and portable environment across simulation and emulation. Develop test plans to verify hardware building blocks, design macros and standard interfaces (PCIe, DDR, USB, I2C, SPI, etc). Own end-to-end DV tasks from coding test benches and test cases, write assertions, run simulations and achieve all coverage goals. Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches. Develop and maintain emulation environment to collect metrics related to emulation environment. Will need to be in San Diego full time, 5 days a week.
Security and citizenship requirements
Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information. Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.
Required Qualifications
5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture
5+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows
Note: Relevant experience of 2-3+ years in any of the mentioned domain - Design/Verification/Implementation.
Preferred Qualifications
Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.
Strong SystemVerilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
Good understanding of chip-level functional model building
Good understanding of OOP concepts; Experience in HVL such as SystemVerilog, UVM/OVM & SystemC
Knowledge of Behavioral and Structural models and familiarity with simulation environments
Experience with make-based build flows and Xilinx Vivado tools
Experience with cm tools such as Git and Gerrit
Experience in formal / static verification methodologies is a plus
Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs
Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog
Experience with C/C++ DPI transactors and monitors
Develop and maintain emulation environment to collect metrics related to emulation environment
Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors
Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations
Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures
Experience with debugging tools such as JTAG and lab test equipment (logic analyzers, oscilloscopes, signal generators, etc.)
Experience with GLS, and scripting languages such as Perl, Python is a plus
Linux OS proficiency
The ideal candidate would be a self-starter with strong initiative, discipline, motivation, and a focus on quality.
The candidate must be a team player and be flexible and open to a variety of task assignments within the team.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
EEO and Benefits
Qualcomm is an equal opportunity employer. Qualcomm is committed to providing an accessible process for individuals with disabilities during the application/hiring process. For accommodations, please contact disability-accommodations@qualcomm.com. Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Pay range and Other Compensation & Benefits: $104,100.00 - $173,400.00
The pay range reflects a broad minimum to maximum for the location. Salary is one component of total compensation, which may include discretionary bonuses and RSU grants. Benefits details are discussed with your recruiter.
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