PCIe RTL Design Engineer for TPU Accelerators

A leading tech company based in Sunnyvale, CA is seeking a PCIe Design Engineer to lead the design of high-performance ASICs for AI/ML hardware acceleration. The role involves RTL development, managing comprehensive documentation, and integrating subsystem functionality within data center accelerators. Candidates should hold a Bachelor's degree and possess significant experience in ASIC design, specifically with PCIe logic. The position includes a competitive salary range and opportunities for growth within a collaborative environment.
#J-18808-Ljbffr