Senior RTL Design Engineer – Silicon ASIC/FPGA

A leading aerospace company in Sunnyvale, CA is seeking a motivated SR. RTL DESIGN ENGINEER to develop next-generation FPGAs and ASICs for space applications. The role involves designing architectures, implementing RTL, and collaborating with cross-disciplinary teams to expand Starlink's capabilities. Candidates should have a Bachelor’s degree in a relevant engineering field and at least 5 years of RTL implementation experience. A competitive compensation package is offered, including stock options and comprehensive benefits.
#J-18808-Ljbffr