Senior FE Design & Timing Engineer

A leading technology company in California is seeking a senior engineer for their wireless silicon development team. The role involves generating static timing constraints and utilizing scripting skills, with a focus on ASIC design. Candidates must have a BS degree and at least 10 years of experience in the field. In addition to a competitive salary range of $181,100 to $318,400, various employee benefits are offered, including stock options and comprehensive medical coverage.
#J-18808-Ljbffr