IC Package Design Engineer - SoC/SiP Layout & Verification

A leading technology corporation in Santa Clara is seeking an IC Package Design Engineer to drive innovative packaging solutions for consumer electronics. The role requires strong expertise in physical design, coordination across teams, and knowledge of advanced packaging technologies. Applicants should be familiar with Cadence Allegro tools and have a solid foundation in engineering principles. Competitive compensation and comprehensive benefits included.
#J-18808-Ljbffr