Senior ASIC RTL Design Engineer — Power‑Aware IP & Subsystems

A leading semiconductor company based in Santa Clara is seeking a Digital Design Engineer to join their SBIO front-end team. In this role, you will design RTL for high-speed digital blocks and work collaboratively with architecture, IP design, and product engineering teams. Ideal candidates should have experience in digital design, processor architecture, and verification, along with related academic credentials. This position plays a crucial role in achieving successful SOC product delivery.
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