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Design Engineer I - DSP & High-Speed Serdes

Cadence Design Systems, San Jose, CA, United States


A leading electronic design automation company is seeking a Design Engineer I in San Jose, California. The role involves DSP algorithm design for high-speed serdes, modeling end-to-end systems that include analog and digital hardware, and verification using lab measurements. The annual salary ranges from $88,900 to $165,100, with potential bonuses and benefits. Ideal candidates will possess a strong foundation in both hardware and software aspects of semiconductor design.
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