Senior IP Physical Design Lead — RTL to GDSII

A leading chiplet startup in San Francisco is seeking a Sr Staff / Principal Physical Design Engineer to innovate and drive the development of cutting-edge ASICs. This role offers the opportunity to oversee the entire design flow from RTL to GDSII while working with a team of experts. Candidates should have a strong background in physical design, timing closure, and mixed signal integration. Excellent communication and leadership skills are essential for ensuring alignment across engineering teams and successful project execution.
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