Silicon Design Engineer
AMD, San Jose, CA, United States
The Role
This is an exciting opportunity to work in the AMD SOC Verification Team as Silicon Design Verification Engineer where you will work with a team and experts in verification.
The Person
The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and other aspects of verification such as performance verification, power aware verification.
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Key Responsibilities
Work with senior verification engineers and create test plans for complex IP designs.
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner.
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks and close the coverage.
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design
Responsible for verification quality metrics like pass rates, code coverage and functional coverage
Preferred Experience
Project level experience with design concepts and RTL implementation for same
Good understanding of computer organization/architecture and digital logic fundamentals
Knowledge of object oriented concepts and programming languages like System Verilog, C++
Hands on Python scripting for automation
Prior design/verification industry experience is a plus with hands on experience on UVM
Academic Credentials
Masters degree in computer engineering/Electrical Engineering
Location
San Jose, CA
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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This is an exciting opportunity to work in the AMD SOC Verification Team as Silicon Design Verification Engineer where you will work with a team and experts in verification.
The Person
The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and other aspects of verification such as performance verification, power aware verification.
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Key Responsibilities
Work with senior verification engineers and create test plans for complex IP designs.
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner.
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks and close the coverage.
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design
Responsible for verification quality metrics like pass rates, code coverage and functional coverage
Preferred Experience
Project level experience with design concepts and RTL implementation for same
Good understanding of computer organization/architecture and digital logic fundamentals
Knowledge of object oriented concepts and programming languages like System Verilog, C++
Hands on Python scripting for automation
Prior design/verification industry experience is a plus with hands on experience on UVM
Academic Credentials
Masters degree in computer engineering/Electrical Engineering
Location
San Jose, CA
This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
#J-18808-Ljbffr