Silicon Design Verification Engineer - UVM & Formal Expert

A leading semiconductor company in San Jose, CA, is seeking a Silicon Design Verification Engineer for the AMD SOC Verification Team. This role involves creating test plans, designing testbenches using System Verilog and UVM, and enhancing verification environments. The ideal candidate will hold a Master's degree in a relevant field and possess strong skills in digital logic and programming languages. Applicants should be prepared for a dynamic work environment that promotes inclusion and diversity.
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