Design Verification Lead
JDWK, Inc., Austin, TX, United States
We’re a small, fast-moving team developing RISC‑V–based SoCs and the software infrastructure to automate chip design. Our goal is to make advanced silicon development faster, smarter, and more accessible.
We’re looking for a Design Verification Engineer who can take ownership of the verification environment for our SoC and RISC‑V CPU core. You’ll be responsible for building a scalable, automated verification framework that continuously validates RTL quality as the design evolves — enabling confident, autonomous design iteration.
This is a high-impact, hands‑on role at the center of our hardware development flow.
Role Overview
As the Design Verification Engineer, you’ll architect, implement, and maintain the SoC-level and CPU-level verification environment. You will develop the testbench infrastructure, write test scenarios and coverage models, and integrate regression and continuous verification into our CI flow.
You’ll work closely with RTL designers, FPGA engineers, and software developers to ensure the entire hardware‑software stack is verified at both the simulation and system levels.
Key Responsibilities
Own the verification environment for the RISC‑V CPU and SoC, from architecture to execution.
Develop and maintain UVM/SystemVerilog or equivalent testbench infrastructure for block-level and SoC-level verification.
Design constrained‑random, directed, and coverage-driven tests to validate functional correctness, performance, and corner cases.
Integrate verification flows into CI/CD pipelines for automated and continuous regression testing.
Collaborate with design engineers to identify test requirements, implement checkers, and add assertions.
Monitor verification coverage metrics and drive closure.
Leverage FPGA prototyping for accelerated testing, firmware validation, and hardware/software co‑verification.
Collaborate with software and systems teams to develop test firmware, diagnostic tools, and bring‑up tests.
Document methodologies and help establish best practices for verification automation and infrastructure.
Requirements
5+ years of experience in ASIC/SoC design verification, including at least one full project cycle from environment bring‑up to tape‑out.
Strong proficiency in SystemVerilog/UVM or equivalent methodologies for testbench development.
Hands‑on experience verifying RISC‑V or other CPU cores, memory subsystems, and on‑chip interconnects.
Proficiency with simulation, coverage, and debugging tools (e.g., VCS, Xcelium, Questa).
Experience developing and managing regression and CI flows (Jenkins, GitLab CI, or similar).
Ability to script and automate using Python, Tcl, or shell scripting.
Knowledge of FPGA-based verification and bring‑up.
Understanding of software‑based validation (e.g., running firmware or bare‑metal tests on emulation or FPGA).
Strong analytical and debugging skills, with attention to detail and a proactive mindset.
Comfort working in a startup environment, handling multiple responsibilities and evolving priorities.
Preferred Qualifications
Familiarity with RISC‑V architecture and open‑source cores (Rocket, CVA6, Ibex, etc.).
Experience with formal verification tools and property checking.
What We Offer
The opportunity to own verification strategy and infrastructure for a complete RISC‑V SoC.
A broad and challenging role at the intersection of hardware, software, and automation.
High visibility and technical impact in a small, expert team.
Flexible work arrangements and PTO.
Competitive compensation and benefits.
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We’re looking for a Design Verification Engineer who can take ownership of the verification environment for our SoC and RISC‑V CPU core. You’ll be responsible for building a scalable, automated verification framework that continuously validates RTL quality as the design evolves — enabling confident, autonomous design iteration.
This is a high-impact, hands‑on role at the center of our hardware development flow.
Role Overview
As the Design Verification Engineer, you’ll architect, implement, and maintain the SoC-level and CPU-level verification environment. You will develop the testbench infrastructure, write test scenarios and coverage models, and integrate regression and continuous verification into our CI flow.
You’ll work closely with RTL designers, FPGA engineers, and software developers to ensure the entire hardware‑software stack is verified at both the simulation and system levels.
Key Responsibilities
Own the verification environment for the RISC‑V CPU and SoC, from architecture to execution.
Develop and maintain UVM/SystemVerilog or equivalent testbench infrastructure for block-level and SoC-level verification.
Design constrained‑random, directed, and coverage-driven tests to validate functional correctness, performance, and corner cases.
Integrate verification flows into CI/CD pipelines for automated and continuous regression testing.
Collaborate with design engineers to identify test requirements, implement checkers, and add assertions.
Monitor verification coverage metrics and drive closure.
Leverage FPGA prototyping for accelerated testing, firmware validation, and hardware/software co‑verification.
Collaborate with software and systems teams to develop test firmware, diagnostic tools, and bring‑up tests.
Document methodologies and help establish best practices for verification automation and infrastructure.
Requirements
5+ years of experience in ASIC/SoC design verification, including at least one full project cycle from environment bring‑up to tape‑out.
Strong proficiency in SystemVerilog/UVM or equivalent methodologies for testbench development.
Hands‑on experience verifying RISC‑V or other CPU cores, memory subsystems, and on‑chip interconnects.
Proficiency with simulation, coverage, and debugging tools (e.g., VCS, Xcelium, Questa).
Experience developing and managing regression and CI flows (Jenkins, GitLab CI, or similar).
Ability to script and automate using Python, Tcl, or shell scripting.
Knowledge of FPGA-based verification and bring‑up.
Understanding of software‑based validation (e.g., running firmware or bare‑metal tests on emulation or FPGA).
Strong analytical and debugging skills, with attention to detail and a proactive mindset.
Comfort working in a startup environment, handling multiple responsibilities and evolving priorities.
Preferred Qualifications
Familiarity with RISC‑V architecture and open‑source cores (Rocket, CVA6, Ibex, etc.).
Experience with formal verification tools and property checking.
What We Offer
The opportunity to own verification strategy and infrastructure for a complete RISC‑V SoC.
A broad and challenging role at the intersection of hardware, software, and automation.
High visibility and technical impact in a small, expert team.
Flexible work arrangements and PTO.
Competitive compensation and benefits.
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