RTL Design Engineer
ALTEN, California, MO, United States
Responsibilities Develop RTL for processor datapath components
Design blocks such as: ALU, Load/Store units, Vector / Matrix execution units, Register files, Instruction decode / execution pipelines
Implement microarchitecture in Verilog/SystemVerilog
Work closely with verification teams to ensure design correctness
Support front-end design flows (lint, CDC, synthesis)
Requirements 5+ years RTL design experience
Strong Verilog / SystemVerilog
Experience with CPU datapath design
Familiarity with vector or matrix compute units
Preferred RISC-V architecture knowledge
Experience in processor pipeline design
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Design blocks such as: ALU, Load/Store units, Vector / Matrix execution units, Register files, Instruction decode / execution pipelines
Implement microarchitecture in Verilog/SystemVerilog
Work closely with verification teams to ensure design correctness
Support front-end design flows (lint, CDC, synthesis)
Requirements 5+ years RTL design experience
Strong Verilog / SystemVerilog
Experience with CPU datapath design
Familiarity with vector or matrix compute units
Preferred RISC-V architecture knowledge
Experience in processor pipeline design
#J-18808-Ljbffr