Senior RTL Design Engineer – CPU Datapath & Vector Units

A technology consulting firm in California is seeking an experienced RTL Designer to focus on processor datapath components and microarchitecture. The ideal candidate will have over 5 years of RTL design experience, strong Verilog/SystemVerilog skills, and an understanding of CPU datapath design. This role involves collaboration with verification teams and support for front-end design flows, ensuring high-quality implementations.
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