Nanoscale DRAM Design Engineer | DTCO Innovator

A leading semiconductor company in Boise, Idaho, is seeking a Design Engineer to join their DRAM Design & Technology Co-Optimization team. This role involves developing and optimizing nanoscale DRAM circuit designs, collaborating across teams, and contributing to innovations in memory technology. Candidates should have a Master's in Electrical Engineering or Applied Physics and experience in CMOS design and memory analysis. Comprehensive benefits and career growth opportunities are offered.
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