Staff Engineer: Verilog/UVM Design Verification

A global memory technology company is seeking a Design Verification Engineer in Boise, Idaho. The candidate should possess strong knowledge in Verilog and System Verilog languages, with a minimum of 6 years experience in Design Verification. The role involves writing UVM test cases and working with cross-functional teams. Knowledge of protocols like PCIe, UCIe, or DDR is advantageous, and usage of AI skills is mandatory. Join a leader in memory and storage solutions that enrich life for all.
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