Lead PLL Design Engineer — Mixed-Signal FinFET ASIC

A leading semiconductor company in Folsom, CA is searching for an experienced Circuit Design Engineer to join their PLL design team. Responsibilities include designing complex PLL blocks, performing verification flows, and collaborating with mask design engineers. The ideal candidate should have solid knowledge of Mixed Signal Circuit Design, proficiency in industry standard tools, and strong communication skills. A Master’s in Electrical Engineering or equivalent is preferred. This position does not offer visa sponsorship.
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