PLL Architect and Design Engineer
Chelsea Search Group, Austin, TX, United States
PLL Architect and Design Engineer
Responsibilities
Address challenges in advanced node technologies, such as self‑heating, electromigration, voltage‑controlled oscillator (VCO) linearization and device‑level noise optimization.
Architect, design and simulate analog/mixed‑signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, loop filters) at transistor level using tools such as Cadence Virtuoso and Spectre.
Be responsible for PLL bring‑up in the lab and conduct performance characterization using state‑of‑the‑art lab equipment.
Conduct comprehensive system‑level simulations and validation for PLL integration into advanced transceiver technologies.
Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies.
Understand trade‑offs between different PLL topologies (integer‑N, fractional‑N, all‑digital/ADPLL) to meet specifications for power, area, jitter, and frequency range.
Required Skills & Experience
Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design and production‑level tape‑out experience.
Deep understanding of phase noise analysis, VCO design, LDOs, and supporting circuitry associated with PLLs.
Must have extensive experience with advanced node technologies (16 nm/12 nm, 7 nm, 5 nm, 3 nm, 2 nm processes).
Proficient in Cadence Virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system‑level modelling.
Strong communication and documentation skills.
#J-18808-Ljbffr
Responsibilities
Address challenges in advanced node technologies, such as self‑heating, electromigration, voltage‑controlled oscillator (VCO) linearization and device‑level noise optimization.
Architect, design and simulate analog/mixed‑signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, loop filters) at transistor level using tools such as Cadence Virtuoso and Spectre.
Be responsible for PLL bring‑up in the lab and conduct performance characterization using state‑of‑the‑art lab equipment.
Conduct comprehensive system‑level simulations and validation for PLL integration into advanced transceiver technologies.
Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies.
Understand trade‑offs between different PLL topologies (integer‑N, fractional‑N, all‑digital/ADPLL) to meet specifications for power, area, jitter, and frequency range.
Required Skills & Experience
Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design and production‑level tape‑out experience.
Deep understanding of phase noise analysis, VCO design, LDOs, and supporting circuitry associated with PLLs.
Must have extensive experience with advanced node technologies (16 nm/12 nm, 7 nm, 5 nm, 3 nm, 2 nm processes).
Proficient in Cadence Virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system‑level modelling.
Strong communication and documentation skills.
#J-18808-Ljbffr