RTL Design Engineer – Mixed-Signal ASICs & Silicon Bring-Up

Teradyne is seeking an RTL Designer for its Silicon Technology Engineering team in North Reading, MA. This role involves developing advanced node ASICs and working collaboratively with an Analog team to ensure high-quality RTL designs. Candidates should have a BSEE or MSEE and 5+ years of experience in RTL design, with skills in Verilog, timing constraints, and high-speed data paths. The position offers a competitive salary and various comprehensive benefits including medical and retirement plans.
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