RTL Design Engineer
Teradyne, North Reading, MA, United States
Location: North Reading, MA, US
Opportunity Overview
Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next‑generation products such as SOC and Memory Test Instruments. Teradyne’s products must be ahead of the semiconductor industry to enable customers to ship production chips/products. You will join a best‑in‑class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne’s next‑generation large Mixed‑Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bring‑up, and will have cutting‑edge AI tools available to optimize your productivity.
Responsibilities
Develop specifications, micro‑architecture, and RTL design of mission‑critical blocks in collaboration with the chip architect.
Integrate industry‑standard and Teradyne custom IPs.
Collaborate with the verification team on test plans, debug support, and coverage closure to ensure high‑quality RTL and first‑pass silicon success.
Provide timing constraints and STA support to the Physical Design team through timing closure.
Offer post‑silicon lab bring‑up and debug support.
Qualifications
BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
Extensive logic design experience writing RTL in Verilog.
Experience designing state machines, FIFOs, high‑speed data paths, arbitration logic, and DFT.
Experience with logic synthesis and timing constraints.
Experience with clock domain crossings (CDC) and static timing analysis (STA).
Experience with high‑speed memory and serial interfaces.
Experience with automation through scripting such as Python, Tcl & Make.
Compensation
The base salary range for this role is $123,100 - $196,900. This range is a good‑faith estimate, and the amount of base salary will correspond with experience and skill set. The range can also fluctuate depending on demand and location.
Incentive Plan
This job is eligible for discretionary bonus(es) based on financial performance.
Benefits
Teradyne offers a variety of comprehensive health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.
We are an equal‑opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment.
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Opportunity Overview
Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next‑generation products such as SOC and Memory Test Instruments. Teradyne’s products must be ahead of the semiconductor industry to enable customers to ship production chips/products. You will join a best‑in‑class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne’s next‑generation large Mixed‑Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bring‑up, and will have cutting‑edge AI tools available to optimize your productivity.
Responsibilities
Develop specifications, micro‑architecture, and RTL design of mission‑critical blocks in collaboration with the chip architect.
Integrate industry‑standard and Teradyne custom IPs.
Collaborate with the verification team on test plans, debug support, and coverage closure to ensure high‑quality RTL and first‑pass silicon success.
Provide timing constraints and STA support to the Physical Design team through timing closure.
Offer post‑silicon lab bring‑up and debug support.
Qualifications
BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
Extensive logic design experience writing RTL in Verilog.
Experience designing state machines, FIFOs, high‑speed data paths, arbitration logic, and DFT.
Experience with logic synthesis and timing constraints.
Experience with clock domain crossings (CDC) and static timing analysis (STA).
Experience with high‑speed memory and serial interfaces.
Experience with automation through scripting such as Python, Tcl & Make.
Compensation
The base salary range for this role is $123,100 - $196,900. This range is a good‑faith estimate, and the amount of base salary will correspond with experience and skill set. The range can also fluctuate depending on demand and location.
Incentive Plan
This job is eligible for discretionary bonus(es) based on financial performance.
Benefits
Teradyne offers a variety of comprehensive health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.
We are an equal‑opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment.
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