Sr. Staff HW Engineer – ASIC Implementation
Arycs Technologies, Los Gatos, CA, United States
Location: Cleveland, OH or Los Gatos, CA
Position Overview
We are seeking an experienced Staff ASIC Implementation Engineer to lead and drive digital implementation across our DSP ASIC programs. This role drives RTL integration through synthesis, timing analysis, and tapeout readiness, including evaluating and optimizing for performance, power, and area (PPA) while working with RTL and verification teams and coordinating with external backend partners responsible for place‑and‑route through GDS release. This is a hands‑on technical leadership role, coordinating implementation efforts across small internal engineering teams and external backend partners to deliver successful first‑pass silicon.
Key Responsibilities
Digital Implementation
Perform and debug lint, CDC, and RDC checks, including development of automation and scripts to run and analyze results
Drive RTL‑to‑synthesis implementation flows, including development of automation and scripts to support these flows
Develop timing constraints (SDC) ensuring correctness and alignment with backend implementation and timing closure objectives
Perform synthesis to support design exploration and PPA optimization
Develop and maintain power intent specifications (UPF) and support low‑power implementation
Perform RTL power analysis and optimization, and assist with gate‑level power analysis, debugging, and RTL‑to‑gate power correlation
Analyze timing reports to identify root causes of timing violations and drive timing closure
Work with RTL engineers to identify and implement RTL changes required to meet timing, power, and implementation requirements
Support and lead design readiness reviews prior to backend implementation kickoff
Backend Coordination
Serve as the primary technical interface with external backend implementation teams
Provide technical oversight of backend place‑and‑route activities and guide timing, congestion, and implementation closure strategy
Review backend implementation metrics, timing closure progress, and physical design results
Track and coordinate resolution of implementation issues identified during physical design
Timing Closure and Tapeout Readiness
Support timing closure and design optimization across RTL and implementation flows
Ensure designs meet timing, power, and integration requirements prior to tapeout
Support final integration, signoff readiness, and tapeout preparation
Cross‑Team Collaboration
Work closely with RTL design teams, verification teams, and backend implementation vendors
Coordinate implementation activities across small internal engineering teams and external backend partners
Coordinate implementation activities and track engineering progress using project management tools (e.g., Jira), including organizing engineering sprints and maintaining visibility of implementation tasks across internal and external teams
Interface with project management teams to support development and tracking of implementation schedules, including defining tasks, milestones, and resource requirements using industry‑standard planning tools (e.g., Microsoft Project or similar)
Identify, communicate, and help drive resolution of technical risks that may impact implementation schedules or tapeout readiness
Implementation Methodology and Tool Flow
Develop and maintain digital implementation flows, automation, and supporting scripts
Improve synthesis, timing analysis, and integration methodologies
Collaborate with EDA vendors to resolve tool issues and improve flow efficiency
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
10+ years of experience in ASIC digital implementation
Strong experience with RTL‑to‑synthesis flows (Design Compiler, Fusion Compiler)
Deep understanding of static timing analysis and timing closure (PrimeTime)
Experience with low‑power implementation methodologies including UPF
Experience performing RTL power analysis and optimization (RTL Architect, PrimePower, PrimePower RTL)
Experience debugging post‑layout timing issues and guiding resolution with backend implementation teams
Experience supporting or driving designs through successful ASIC tapeout
Strong scripting skills (Tcl, Python) for automation and analysis of implementation flows
Preferred Qualifications
Familiarity with place‑and‑route and physical design flows
Experience working with external backend implementation vendors
Experience with high‑throughput datapath or DSP‑based designs
Familiarity with advanced technology nodes (7nm and below)
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Position Overview
We are seeking an experienced Staff ASIC Implementation Engineer to lead and drive digital implementation across our DSP ASIC programs. This role drives RTL integration through synthesis, timing analysis, and tapeout readiness, including evaluating and optimizing for performance, power, and area (PPA) while working with RTL and verification teams and coordinating with external backend partners responsible for place‑and‑route through GDS release. This is a hands‑on technical leadership role, coordinating implementation efforts across small internal engineering teams and external backend partners to deliver successful first‑pass silicon.
Key Responsibilities
Digital Implementation
Perform and debug lint, CDC, and RDC checks, including development of automation and scripts to run and analyze results
Drive RTL‑to‑synthesis implementation flows, including development of automation and scripts to support these flows
Develop timing constraints (SDC) ensuring correctness and alignment with backend implementation and timing closure objectives
Perform synthesis to support design exploration and PPA optimization
Develop and maintain power intent specifications (UPF) and support low‑power implementation
Perform RTL power analysis and optimization, and assist with gate‑level power analysis, debugging, and RTL‑to‑gate power correlation
Analyze timing reports to identify root causes of timing violations and drive timing closure
Work with RTL engineers to identify and implement RTL changes required to meet timing, power, and implementation requirements
Support and lead design readiness reviews prior to backend implementation kickoff
Backend Coordination
Serve as the primary technical interface with external backend implementation teams
Provide technical oversight of backend place‑and‑route activities and guide timing, congestion, and implementation closure strategy
Review backend implementation metrics, timing closure progress, and physical design results
Track and coordinate resolution of implementation issues identified during physical design
Timing Closure and Tapeout Readiness
Support timing closure and design optimization across RTL and implementation flows
Ensure designs meet timing, power, and integration requirements prior to tapeout
Support final integration, signoff readiness, and tapeout preparation
Cross‑Team Collaboration
Work closely with RTL design teams, verification teams, and backend implementation vendors
Coordinate implementation activities across small internal engineering teams and external backend partners
Coordinate implementation activities and track engineering progress using project management tools (e.g., Jira), including organizing engineering sprints and maintaining visibility of implementation tasks across internal and external teams
Interface with project management teams to support development and tracking of implementation schedules, including defining tasks, milestones, and resource requirements using industry‑standard planning tools (e.g., Microsoft Project or similar)
Identify, communicate, and help drive resolution of technical risks that may impact implementation schedules or tapeout readiness
Implementation Methodology and Tool Flow
Develop and maintain digital implementation flows, automation, and supporting scripts
Improve synthesis, timing analysis, and integration methodologies
Collaborate with EDA vendors to resolve tool issues and improve flow efficiency
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
10+ years of experience in ASIC digital implementation
Strong experience with RTL‑to‑synthesis flows (Design Compiler, Fusion Compiler)
Deep understanding of static timing analysis and timing closure (PrimeTime)
Experience with low‑power implementation methodologies including UPF
Experience performing RTL power analysis and optimization (RTL Architect, PrimePower, PrimePower RTL)
Experience debugging post‑layout timing issues and guiding resolution with backend implementation teams
Experience supporting or driving designs through successful ASIC tapeout
Strong scripting skills (Tcl, Python) for automation and analysis of implementation flows
Preferred Qualifications
Familiarity with place‑and‑route and physical design flows
Experience working with external backend implementation vendors
Experience with high‑throughput datapath or DSP‑based designs
Familiarity with advanced technology nodes (7nm and below)
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