Staff Design Verification Engineer
Renesas Electronics Corporation, Austin, TX, United States
Responsibilities
Plan the verification of complex SoC & design blocks by fully understanding the design specification
Interact with design/system engineers to identify important verification scenarios
Create and enhance constrained-random verification environments using System Verilog.
Create and support UVM compliant test-bench architecture
Formally verify designs with SVA and industry leading formal tools
Identify and write various coverage metrics for stimulus and corner-cases
Build reusable DV infrastructure components for both block and top-level environments
Debug tests in collaboration with design engineering staff
Build verification tools for system automation, regressions, and reporting
Qualifications
BS/MSEE & relevant work experience
5-8 years minimum experience with System Verilog, SVA and functional coverage
Deep understanding of event-driven simulator-based modeling techniques
Advanced knowledge of mixed signal concepts and digital-analog interfaces
Developed and executed several comprehensive SoC and block level verification plans
Worked on commercially successful IC’s
Strong problem-solving abilities
Clear written and verbal communications, including code documentation
Preferred Qualifications
Experience in the verification of power management ICs, high speed interfaces, or peripheral controllers
Strong knowledge of VIP integration of High-speed interface protocols
Experience in SVRNM modelling and verification
Prior experience in the development of verification strategy, test design, and test infrastructure
Proficiency with a scripting language like Python/Perl
Familiarity with FPGA emulation techniques
Understanding of firmware (C language) based test routines to run on embedded MC
Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.
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Plan the verification of complex SoC & design blocks by fully understanding the design specification
Interact with design/system engineers to identify important verification scenarios
Create and enhance constrained-random verification environments using System Verilog.
Create and support UVM compliant test-bench architecture
Formally verify designs with SVA and industry leading formal tools
Identify and write various coverage metrics for stimulus and corner-cases
Build reusable DV infrastructure components for both block and top-level environments
Debug tests in collaboration with design engineering staff
Build verification tools for system automation, regressions, and reporting
Qualifications
BS/MSEE & relevant work experience
5-8 years minimum experience with System Verilog, SVA and functional coverage
Deep understanding of event-driven simulator-based modeling techniques
Advanced knowledge of mixed signal concepts and digital-analog interfaces
Developed and executed several comprehensive SoC and block level verification plans
Worked on commercially successful IC’s
Strong problem-solving abilities
Clear written and verbal communications, including code documentation
Preferred Qualifications
Experience in the verification of power management ICs, high speed interfaces, or peripheral controllers
Strong knowledge of VIP integration of High-speed interface protocols
Experience in SVRNM modelling and verification
Prior experience in the development of verification strategy, test design, and test infrastructure
Proficiency with a scripting language like Python/Perl
Familiarity with FPGA emulation techniques
Understanding of firmware (C language) based test routines to run on embedded MC
Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.
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