Senior Design Verification Engineer SystemVerilog/UVM

A leading technology company is seeking a Senior Design Verification Engineer to explore innovative hardware designs. This role involves defining verification methodologies, implementing test plans, and collaborating with cross-functional teams. Candidates should have a Bachelor's degree in Electrical Engineering, along with at least 7 years of experience in design verification using SystemVerilog and UVM. The position offers competitive salary and comprehensive benefits, supported by a creative work environment in Sunnyvale, California.
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