Principal Digital Design Engineer (f/m/d)
Renesas Electronics Corporation, Greenlawn, NY, United States
Job Description
Renesas is seeking a Principal Digital Design Engineer to join our SoC development team in Zurich. This is a senior technical leadership position with direct influence over digital architecture decisions, design methodology, and product direction for next-generation power management and connectivity SoCs.
The role demands deep expertise in digital IC design, a proven track record of silicon delivery, and the ability to operate effectively across engineering disciplines and organisational boundaries.
Key Responsibilities
Architecture & Design
Define digital architecture for complex mixed‑signal SoCs (power management, wireless power, connectivity)
Lead design and integration of digital subsystems: control logic, FSMs, datapaths, embedded microcontroller subsystems, register maps, and bus architectures (AHB/APB or equivalent)
Own RTL development end‑to‑end, from micro‑architecture specification through to silicon
Low‑Power & Physical Implementation
Define and drive low‑power strategies including clock gating, power domain partitioning, and UPF flows
Collaborate with physical design teams on synthesis, timing closure, and PPA optimisation
Cross‑Functional Collaboration
Work closely with analog/mixed‑signal teams on AMS interfaces
Partner with verification teams on coverage‑driven verification (UVM)
Support silicon bring‑up, debug, and product validation
Technical Leadership
Author and review micro‑architecture specifications and design guidelines
Define and enforce RTL coding standards
Mentor junior and mid‑level engineers
Contribute to IP reuse strategy, design methodology, and product roadmap
Qualifications
Required Qualifications
MSc or PhD in Electrical Engineering or a related discipline
10+ years of experience in digital IC and SoC design
Expert‑level RTL design skills in Verilog/SystemVerilog
Strong background in SoC architecture, integration, synthesis, and timing closure
Solid knowledge of low‑power design techniques, clock domain crossing (CDC), reset strategies, and design‑for‑test (DFT)
Hands‑on experience with industry‑standard EDA tools (Synopsys, Cadence, or equivalent)
Multiple successful silicon tape‑outs as a lead or senior contributor
Fluent English communication skills
Preferred Qualifications
Experience with mixed‑signal or power IC design (BCD process, wireless power)
Familiarity with embedded CPU subsystems (ARM Cortex‑M or equivalent)
Exposure to UVM‑based verification environments
Scripting proficiency in Python or Tcl
Experience in distributed or cross‑site engineering teams
Prior technical ownership at block or chip level
What We Offer
High‑impact role in the design of advanced power and connectivity SoCs
Technical leadership visibility with a clear path toward Distinguished Engineer or Technical Fellow
Collaborative, international engineering environment
Competitive compensation and comprehensive benefits package
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
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Renesas is seeking a Principal Digital Design Engineer to join our SoC development team in Zurich. This is a senior technical leadership position with direct influence over digital architecture decisions, design methodology, and product direction for next-generation power management and connectivity SoCs.
The role demands deep expertise in digital IC design, a proven track record of silicon delivery, and the ability to operate effectively across engineering disciplines and organisational boundaries.
Key Responsibilities
Architecture & Design
Define digital architecture for complex mixed‑signal SoCs (power management, wireless power, connectivity)
Lead design and integration of digital subsystems: control logic, FSMs, datapaths, embedded microcontroller subsystems, register maps, and bus architectures (AHB/APB or equivalent)
Own RTL development end‑to‑end, from micro‑architecture specification through to silicon
Low‑Power & Physical Implementation
Define and drive low‑power strategies including clock gating, power domain partitioning, and UPF flows
Collaborate with physical design teams on synthesis, timing closure, and PPA optimisation
Cross‑Functional Collaboration
Work closely with analog/mixed‑signal teams on AMS interfaces
Partner with verification teams on coverage‑driven verification (UVM)
Support silicon bring‑up, debug, and product validation
Technical Leadership
Author and review micro‑architecture specifications and design guidelines
Define and enforce RTL coding standards
Mentor junior and mid‑level engineers
Contribute to IP reuse strategy, design methodology, and product roadmap
Qualifications
Required Qualifications
MSc or PhD in Electrical Engineering or a related discipline
10+ years of experience in digital IC and SoC design
Expert‑level RTL design skills in Verilog/SystemVerilog
Strong background in SoC architecture, integration, synthesis, and timing closure
Solid knowledge of low‑power design techniques, clock domain crossing (CDC), reset strategies, and design‑for‑test (DFT)
Hands‑on experience with industry‑standard EDA tools (Synopsys, Cadence, or equivalent)
Multiple successful silicon tape‑outs as a lead or senior contributor
Fluent English communication skills
Preferred Qualifications
Experience with mixed‑signal or power IC design (BCD process, wireless power)
Familiarity with embedded CPU subsystems (ARM Cortex‑M or equivalent)
Exposure to UVM‑based verification environments
Scripting proficiency in Python or Tcl
Experience in distributed or cross‑site engineering teams
Prior technical ownership at block or chip level
What We Offer
High‑impact role in the design of advanced power and connectivity SoCs
Technical leadership visibility with a clear path toward Distinguished Engineer or Technical Fellow
Collaborative, international engineering environment
Competitive compensation and comprehensive benefits package
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
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